The present invention relates to a MOS transistor, and more particularly to a MOS transistor with improved means for preventing destruction due to breakdown.
In recent years, the development of a MOS power transistor allows a MOS transistor 1 as shown FIG. 1 to be used as a switching element for switching a power load 2. For example, in a vehicle, it has been proposed that the MOS transistor be applied to the switching of a power load assembled in various vehicles.
A MOS transistor having a structure as shown in FIG. 2 is well known as a prior art MOS transistor. The MOS transistor shown in FIG. 2 is a so-called vertical MOS transistor, for example, which is disclosed in U.S. Pat. No. 4,345,265. Basically, such a MOS transistor comprises a semiconductor substrate 6 including an N+ type region 4 having low specific resistance and to which a drain electrode 3 is joined at a lower surface of the N+ type region 4 and an N type region 5 having high specific resistance and joined to an upper surface side of the N+ type region 4, a plurality of P type well regions 7 having a conductive type opposite that of the substrate 6 and formed at predetermined intervals in the N type region 5 which is located on the upper portion of the substrate 6, N+ type source regions 8 formed in the P type well regions 7, and gate electrodes 10 formed through gate oxide layers 9 of insulating layers formed on the surface of the substrate 6 and the well regions 7 while extending over the N+ type source regions 8 and the N type region 5 of the substrate 6 which is substantially adapted to operate as a drain region. The top surface portion is covered with PSG (phospho-silicate glass) layer 12 except a portion from which a gate electrode 10 is taken out. A source electrode 11 is also joined to P+ type contact regions 13 formed in the P type well regions 7.
Such a MOS transistor is required to have a capability for withstanding a higher voltage due to the necessity of switching a relatively high voltage and high current. Specifically, when the load contains an inductive load such as a motor, a solenoid or the like, the MOS transistor is required to have a sufficient capability for withstanding a high surge voltage so that the MOS transistor is not destroyed by the surge voltage, since the high surge voltage occurs when a load current is cut off.
As is well known, the MOS transistor includes a parasitic zener diode between the source S and the drain D according to its construction. In FIG. 1, a zener diode Z represents the parasitic zener diode. In FIG. 2, the parasitic zener diode is composed of a PN junction formed between the P type well region 7 and the N type drain region 5.
When a voltage (which is a reverse voltage for the PN junction) is applied between the drain and the source, a depletion layer is produced around the junction between the drain region 5 and the well region 7. In FIG. 2, the region of the depletion layer appears between dotted lines 14a and indicated by reference numeral 14. The depletion layer 14 widens as the voltage between the drain and the source increases.
In the prior art MOS transistor shown in FIG. 2, it must be noted that an avalanche breakdown occurs in the junction between the N type drain region 5 and the well region 7 before the depletion layer 14 extending in the N type drain region 5 reaches the N+ drain region 4 and the current caused by the avalanche breakdown tends to concentrate locally. Accordingly, when the avalanche breakdown is produced by the surge voltage or the like, since the current concentrates locally even if the breakdown current flowing between the drain and the source is relatively small, the MOS transistor element would be destroyued by heating due to the current causes.
As will be described in detail about this phenomenon, the depletion layer 14 in the N type drain region 5 contains valleys V between the two adjacent well regions 7 when the extension of the depletion layer 14 is of a small width as shown by the dotted lines in FIG. 2. The electric field applied to the depletion layer 14 tends to concentrate on portions between the valleys V of the depletion layer 14 and the corners of the well regions 7 as shown by arrows E. In this manner, when the electric field applied to the depletion layer 14 concentrates locally, the flow of the current caused by the avalanche breakdown concentrates on the above mentioned portions, so that the MOS transistor element is destroyed due to the heating generated by the concentration of the current.
On the other hand, when a reverse voltage V.sub.R is applied across the PN junction, the extending width W of the depletion layer from the junction is known to be represented by: ##EQU1## where .epsilon. is a specific dielectric constant of the semiconductor, .epsilon..sub.o is the dielectric constant in the vacuum, q is the charge of the electron, and Ni is an impurity concentration of P type or N type semiconductor.
Further, a withstanding voltage of the PN junction is determined by a higher specific resistance (lower impurity concentration) in either P region or N region as well known. Suppose that the lower impurity concentration is Ni, it is known that the voltage BV at which the avalanche breakdown occurs between the PN junction is approximately in inverse proportion to the impurity concentration Ni.
In the prior art vertical MOS transistor shown in FIG. 2, the impurity concentration in the P type well region 7 is higher than the impurity concentration in the N type drain region 5 and the withstanding voltage of the PN junction (the voltage at which the avalanche breakdown occurs) is determined by the impurity concentration in the N type drain region 5. For example, the impurity concentration in the surface of the P type well region 7 is 10.sup.18 /cm.sup.3 and the impurity concentration in the N type drain region 5 is approximately 10.sup.14 -10.sup.15 /cm.sup.3. Accordingly, when the depletion layer extends in the N type drain region 5, the avalanche breakdown of the PN junction occurs at the withstanding voltage corresponding to the concentration in the N type drain region.